A CAD Methodology for Switched Current Analogue IP Cores

Current technology allows for the integration of complete systems onto a single chip. These systems on chip (SoC) are increasingly designed by connecting together large pre-designed and verified modules, called cores, with the advantage being a faster design cycle. The development of third party Intellectual Property (IP) cores is a rapidly expanding industry, and whereas initially these were nearly all digital, analogue IP cores are now representing a greater proportion of this market. In this report we consider issues which should be addressed when designing analogue IP cores, from low-level circuit realisations to high level design methodologies. The switched current (SI) technique can implement analogue functions on the most basic of digital processes and further advantages of high speed and low voltage operation, suggest that this may be particularly suitable for implementing analogue IP cores. In this work, we have considered the design of analogue SI filter cores, these being a fundamental analogue building block. The wave filter design technique has been found particularly suitable as a filter design method as it is easily implemented in SI and the resulting simple architectures lend themselves to automated generation The biggest obstacle to the use of SI circuits is the difficulty associated with their design. A CAD methodology is proposed to address this problem, which comprises of two parts, a hierarchical analogue cell library and a CAD tool. This methodology has been implemented in the form of ‘AutoSIF’, a cell library and tool which facilitates the rapid generation of firm analogue IP filter cores. AutoSIF was developed specifically to allow a designer to gain valuable insight into SI design process and will be expanded to include other major analogue blocks. Through this tool a complete SI wave analogue filter case study has been presented, from specifications right through to transistor level design and full custom analogue layout. AutoSIF was invaluable in the design process and preliminary results from the fabricated chip are particularly promising. A CAD Methodology for Switched Current Analogue IP Cores 2